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ltc3300-2 1 33002f for more information www.linear.com/ltc3300-2 applications typical application features description addressable high efficiency bidirectional multicell battery balancer the lt c ? 3300-2 is a fault-protected controller ic for transformer-based bidirectional active balancing of multi- cell battery stacks. all associated gate drive circuitry, precision current sensing, fault detection circuitry and a robust serial interface with built-in watchdog timer are integrated. each ltc3300-2 can balance up to 6 series-connected battery cells with an input common mode voltage up to 36v. charge from any selected cell can be transferred at high efficiency to or from 12 or more adjacent cells. each ltc3300-2 has an individually addressable serial interface , allowing up to 32 ltc3300-2 devices to interface to one control processor. fault protection features include readback capability, cy - clic redundancy check ( crc) error detection, maximum on-time volt-second clamps, and overvoltage shutoffs. the related ltc3300-1 offers a serial interface that allows the serial ports of multiple ltc3300-1 devices to be daisy- chained without opto-couplers or isolators. high efficiency bidirectional balancing balancer efficiency n bidirectional synchronous flyback balancing of up to 6 li-ion or lifepo 4 cells in series n up to 10a balancing current (set by externals) n integrates seamlessly with the ltc680x family of multicell battery stack monitors n bidirectional architecture minimizes balancing time and power dissipation n up to 92% charge transfer efficiency n stackable architecture enables >800v systems n uses simple 2-winding transformers n 1 mhz serial interface with 4-bit crc packet error checking n individually addressable with 5-bit address n numerous fault protection features n 48- lead exposed pad qfn and lqfp packages n electric vehicles/plug-in hevs n high power ups/grid energy storage systems n general purpose multicell battery stacks l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and isospi is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. serial i/o + cell 1 i charge charge supply charge supply (i charge 1-6) next cell below 33002 ta01a ltc3300-2 ltc3300-2 address n + 1 address n next cell above ? ? + cell 6 + cell 7 + cell 12 i discharge charge return chargereturn (i discharge 1-6) ? ? 4 5 5 4 4 4 4 isolator isolator number of cells (secondary side) 6 80 charge transfer efficiency (%) 85 9590 100 8 10 charge discharge 33001 ta01b 12 dc2064a demo boardi charge = i discharge = 2.5a v cell = 3.6v downloaded from: http:///
ltc3300-2 2 33002f for more information www.linear.com/ltc3300-2 absolute maximum ratings total supply voltage (c6 to v C ) ................................. 36 v input voltage ( relative to v C ) c1 ........................................................... C0.3 v to 6v i1p ....................................................... C0.3 v to 0.3 v i1s, i2s, i3s, i4s, i5s, i6s .................... C0.3 v to 0.3 v csbi , scki , sdi ....................................... C0.3 v to 6v v reg , sdo ............................................... C0.3 v to 6v rtonp , rtons ........... C0.3 v to min [v reg + 0.3 v, 6v] ctrl , boost, wdt .... C0.3 v to min [v reg + 0.3 v, 6v] a 4, a 3, a 2, a 1, a0 ....... C0.3 v to min [v reg + 0.3 v, 6v] (note 1) top view 49 v C uk package 48-lead (7mm 7mm) plastic qfn g6s 1 i6s 2 g5s 3 i5s 4 g4s 5 i4s 6 g3s 7 i3s 8 g2s 9 i2s 10 g1s 11 i1s 12 36 c535 g5p 34 i5p 33 c4 32 g4p 31 i4p 30 c3 29 g3p 28 i3p 27 c2 26 g2p 25 i2p 48 v reg 47 a446 a3 45 a2 44 a1 43 a0 42 boost 41 boost C 40 boost + 39 c638 g6p 37 i6p rtons 13 rtonp 14 ctrl 15 csbi 16scki 17 sdi 18 sdo 19 wdt 20 v C 21 i1p 22 g1p 23 c1 24 t jmax = 150c, ja = 34c/w, jc = 3c/w exposed pad (pin 49) is v C , must be soldered to pcb 12 3 4 5 6 7 8 9 1011 12 3635 34 33 32 31 30 29 28 27 26 25 g6s i6s g5s i5s g4s i4s g3s i3s g2s i2s g1s i1s 1314 15 16 17 18 19 20 21 22 23 24 rtons rtonp ctrl csbiscki sdi sdo wdt v C i1p g1p c1 4847 46 45 44 43 42 41 40 39 38 37 v reg a4a3 a2 a1 a0 boost boost C boost + c6g6p i6p c5g5p i5p c4 g4p i4p c3 g3p i3p c2 g2p i2p top view 49 v C lxe package 48-lead (7mm 7mm) plastic lqfp t jmax = 150c, ja = 20.46c/w, jc = 3.68c/w exposed pad (pin 49) is v C , must be soldered to pcb pin configuration order information lead free finish tape and reel part marking* package description temperature range ltc3300iuk-2#pbf ltc3300iuk-2#trpbf ltc3300uk-2 48-lead (7mm 7mm) plastic qfn C40c to 125c ltc3300huk-2#pbf ltc3300huk-2#trpbf ltc3300uk-2 48-lead (7mm 7mm) plastic qfn C40c to 150c lead free finish tray part marking* package description temperature range ltc3300ilxe-2#pbf ltc3300ilxe-2#pbf ltc3300lxe-2 48-lead (7mm 7mm) plastic elqfp C40c to 125c ltc3300hlxe-2#pbf ltc3300hlxe-2#pbf ltc3300lxe-2 48-lead (7mm 7mm) plastic elqfp C40c to 150c consult lt c marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ voltage between pins c n to c n -1* .............................................. C0.3 v to 6v i n p to c n -1* .......................................... C0.3 v to 0.3 v boost + to c6 .......................................... C0.3 v to 6v sdo current ........................................................... 10 ma g1p, g n p, g1s, g n s, boost C current ............... 200 ma operating junction temperature range ( notes 2, 7) ltc 3300 i -2 ........................................ C40 c to 125 c ltc 3300 h -2 ...................................... C40 c to 150 c storage temperature range .................. C65 c to 150 c * n = 2 to 6 downloaded from: http:///
ltc3300-2 3 33002f for more information www.linear.com/ltc3300-2 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) boost + = 25.2v, c6 = 21.6v, c5 = 18v, c4 = 14.4v, c3 = 10.8v, c2 = 7.2v, c1 = 3.6v, v ? = 0v, unless otherwise noted. symbol parameter conditions min typ max units dc specificationsi q_sd supply current when not balancing (post suspend or pre first execute) measured at c1, c2, c3, c4, c5 measured at c6 measured at boost + 6 0 14 0 1 22 10 a a a i q_active supply current when balancing (note 3) balancing c1 only (note 4 for v C , c2, c6) measured at c1 measured at c2, c3, c4, c5 measured at c6 measured at boost + 250 70 560 0 375 105 840 10 a a a a balancing c2 only (note 4 for c1, c3, c6) measured at c1 measured at c2 measured at c3, c4, c5 measured at c6 measured at boost + C105 C70 250 70 560 0 375 105 840 10 a a a a a balancing c3 only (note 4 for c2, c4, c6) measured at c1, c4, c5 measured at c2 measured at c3 measured at c6 measured at boost + C105 70 C70 250 560 0 105 375 840 10 a a a a a balancing c4 only (note 4 for c3, c5, c6) measured at c1, c2, c5 measured at c3 measured at c4 measured at c6 measured at boost + C105 70 C70 250 560 0 105 375 840 10 a a a a a balancing c5 only (note 4 for c4, c6) measured at c1, c2, c3 measured at c4 measured at c5 measured at c6 measured at boost + C105 70 C70 250 560 0 105 375 840 10 a a a a a balancing c6 only (note 4 for c5, c6, boost + ) measured at c1, c2, c3, c4 measured at c5 measured at c6 measured at boost + (boost = v C ) measured at boost + (boost = v reg ) C105 70 C70 740 60 0 105 1110 90 10 a a a a a v cell|min minimum cell voltage (rising) required for primary gate drive c n to c n ? 1 voltage to balance c n , n = 2 to 6 c1 voltage to balance c1 c n + 1 to c n voltage to balance c n , n = 1 to 5 boost + to c6 voltage to balance c6, boost = v C l l l l 1.8 1.8 1.8 1.8 2 2 2 2 2.2 2.2 2.2 2.2 v v v v v cell|min(hyst) v cell|min comparator hysteresis 70 mv v cell|max maximum cell voltage (rising) before disabling balancing c1, c n to c n ? 1 voltage to balance any cell, n = 2 to 6 l 4.7 5 5.3 v v cell|max(hyst) v cell|max comparator hysteresis 0.5 v v cell | reconnect maximum cell voltage (falling) to re-enable balancing l 4.25 v v reg regulator pin voltage 9v c6 36v, 0ma i load 20ma l 4.4 4.8 5.2 v v reg|por v reg voltage (rising) for power-on reset 4.0 v v reg|min minimum v reg voltage (falling) for secondary gate drive v reg voltage to balance c n , n = 1 to 6 l 3.8 v downloaded from: http:///
ltc3300-2 4 33002f for more information www.linear.com/ltc3300-2 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) boost + = 25.2v, c6 = 21.6v, c5 = 18v, c4 = 14.4v, c3 = 10.8v, c2 = 7.2v, c1 = 3.6v, v ? = 0v, unless otherwise noted. symbol parameter conditions min typ max units i reg_sc regulator pin short circuit current limit v reg = 0v 55 ma v rtonp rtonp servo voltage r rtonp = 20k l 1.158 1.2 1.242 v v rtons rtons servo voltage r rtons = 15k l 1.158 1.2 1.242 v i wdt_rising wdt pin current, balancing r tons = 15k, wdt = 0.5v l 72 80 88 a i wdt_falling wdt pin current as a percentage of i wdt_rising , secondary ov r tons = 15k, wdt = 2v l 85 87.5 90 % v peak_p primary winding peak current sense voltage i1p i n p to c n ? 1 , n = 2 to 6 l l 45 45 50 50 55 55 mv mv v peak_p matching (all 6) [(max C min)/(max + min)] ? 100% l 1.7 5 % v peak_s secondary winding peak current sense voltage i1s i n s to c n ? 1 , n = 2 to 6, ctrl = 0 only l l 45 45 50 50 55 55 mv mv v peak_s matching (all 6) [(max C min)/(max + min)] ? 100% l 0.5 3 % v zero_p primary winding zero current sense voltage (note 5) i1p i n p to c n ? 1 , n = 2 to 6 l l C7 C7 C2 C2 3 3 mv mv v zero_p matching (all 6) normalized to mid-range v peak_p {[(max C min)/2]/(v peak_p|midrange )} ? 100% (note 6) l 1.7 5 % v zero_s secondary winding zero current sense voltage (note 5) i1s i n s to c n C 1, n = 2 to 6, ctrl = 0 only l l C12 C12 C7 C7 C2 C2 mv mv v zero_s matching (all 6) normalized to mid-range v peak_s {[(max C min)/2]/(v peak_s|midrange )} ? 100% (note 6) l 0.5 3 % r boost_l boost C pin pull-down r on measured at 100ma into pin, boost = v reg 2.5 r boost_h boost C pin pull-up r on measured at 100ma out of pin, boost = v reg 4 t sd thermal shutdown threshold (note 7) rising temperature 155 c t hys thermal shutdown hysteresis 10 c timing specifications t r_p primary winding gate drive rise time (10% to 90%) g1p through g6p, c gate = 2500pf 35 70 ns t f_p primary winding gate drive fall time (90% to 10%) g1p through g6p, c gate = 2500pf 20 40 ns t r_s secondary winding gate drive rise time (10% to 90%) g1s, c gate = 2500pf g2s through g6s, ctrl = 0 only, c gate = 2500pf 30 30 60 60 ns ns t f_s secondary winding gate drive fall time (90% to 10%) g1s, c gate = 2500pf g2s through g6s, ctrl = 0 only, c gate = 2500pf 20 20 40 40 ns ns t onp|max primary winding switch maximum on-time r rtonp = 20k (measured at g1p-g6p) l 6 7.2 8.4 s t onp|max matching (all 6) [(max C min)/(max + min)] ? 100% l 1 4 % t ons|max secondary winding switch maximum on-time r rtons = 15k (measured at g1s-g6s) l 1 1.2 1.4 s t ons|max matching (all 6) [(max C min)/(max + min)] ? 100% l 1 4 % t d ly _start delayed start time after new/ different balance command or recovery from voltage/temp fault 2 ms spi port timing specifications t 1 sdi valid to scki rising setup write operation l 10 ns t 2 sdi valid from scki rising hold write operation l 250 ns t 3 scki low l 400 ns t 4 scki high l 400 ns downloaded from: http:///
ltc3300-2 5 33002f for more information www.linear.com/ltc3300-2 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2) boost + = 25.2v, c6 = 21.6v, c5 = 18v, c4 = 14.4v, c3 = 10.8v, c2 = 7.2v, c1 = 3.6v, v ? = 0v, unless otherwise noted. symbol parameter conditions min typ max units t 5 csbi pulse width l 400 ns t 6 scki rising to csbi rising l 100 ns t 7 csbi falling to scki rising l 100 ns t 8 scki falling to sdo valid read operation l 250 ns f clk clock frequency l 1 mhz t wd1 watchdog timer timeout period wdt assertion measured from last valid command byte l 0.75 1.5 2.25 second t wd2 watchdog timer reset time wdt negation measured from last valid command byte l 1.5 5 s digital i/o specificationsv ih digital input voltage high pins csbi, scki, sdi pins ctrl, boost pins a4, a3, a2, a1, a0 pin wdt l l l l v reg C 0.5 v reg C 0.5 v reg C 0.5 2 v v v v v il digital input voltage low pins csbi, scki, sdi pins ctrl, boost pins a4, a3, a2, a1, a0 pin wdt l l l l 0.5 0.5 0.5 0.8 v v v v i ih digital input current high pins csbi, scki, sdi pins ctrl, boost pins a4, a3, a2, a1, a0 pin wdt, timed out C1 C1 C1 C1 0 0 0 0 1 1 1 1 a a a a i il digital input current low pins csbi, scki, sdi pins ctrl, boost pins a4, a3, a2, a1, a0 pin wdt, not balancing C1 C1 C1 C1 0 0 0 0 1 1 1 1 a a a a v ol digital output voltage low pin sdo, sinking 500a; read l 0.3 v i oh digital output current high pin sdo at 6v l 100 na note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3300-2 is tested under pulsed load conditions such that t j t a . the ltc3300i-2 is guaranteed over the C40c to 125c operating junction temperature range and the ltc3300h-2 is guaranteed over the C40c to 150c operating junction temperature. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance. note 3: when balancing more than one cell at a time, the individual cell supply currents can be calculated from the values given in the table as follows: first add the appropriate table entries cell by cell for the balancers that are on. second, for each additional balancer that is on , subtract 70a from the resultant sums for c1, c2, c3, c4, and c5, and 450a from the resultant sum for c6. for example, if all six balancers are on, the resultant current for c1 is [250 C 70 + 70 + 70 + 70 + 70 C 5(70)]a = 110a and for c6 is [560 + 560 + 560 + 560 + 560 + 740 C 5(450)]a = 1290a. note 4: dynamic supply current is higher due to gate charge being delivered at the switching frequency during active balancing. see gate drivers/gate drive comparators and voltage regulator in the operation section for more information on estimating these currents. note 5: the zero current sense voltages given in the table are dc thresholds. the actual zero current sense voltage seen in application will be closer to zero due to the slew rate of the winding current and the finite delay of the current sense comparator. note 6: the mid-range value is the average of the minimum and maximum readings within the group of six.note 7: this ic includes overtemperature protection intended to protect the device during momentary overload conditions. the maximum junction temperature may be exceeded when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. downloaded from: http:///
ltc3300-2 6 33002f for more information www.linear.com/ltc3300-2 typical performance characteristics maximum cell voltage to allow balancing vs temperature v reg load regulation v reg voltage vs temperature c6 supply current when not balancing vs temperature t a = 25c unless otherwise specified. supply current when balancing vs temperature normalized to 25 c minimum cell voltage required for primary gate drive vs temperature v reg por voltage and minimum secondary gate drive vs temperature v reg short-circuit current limit vs temperature v rtonp , v rtons vs temperature temperature (c) C50 i q(sd) (a) 16 18 20 25 75 150 33002 g01 14 12 10 C25 0 50 100 125 c6 = 21.6v temperature (c) C50 0.94 i q(active) /i q(active at 25c) 0.96 0.98 1.00 1.02 0 50 100 150 33002 g02 1.04 1.06 C25 25 75 125 typ = 740a typ = 560a typ = 250a typ = 70a typ = 60a typ = C70a 3.6v per cellmatch curve with table entry temperature (c) C50 1.80 v cell(min) (v) 1.85 1.90 1.95 2.00 0 50 100 150 33002 g03 2.05 2.10 C25 25 75 125 cell voltage rising cell voltage falling temperature (c) C50 4.2 v cell(max) (v) 4.3 4.5 4.6 4.7 5.24.9 0 50 75 lt33002 g04 4.4 5.0 5.1 4.8 C25 25 100 125 150 cell voltage rising cell voltage falling i vreg (ma) 0 v reg (v) 4.8 4.9 5.0 40 33002 g05 4.7 4.6 4.5 5 10 15 20 25 30 35 45 50 t a = 25c c6 = 36v c6 = 9v temperature (c) C50 4.60 v reg (v) 4.61 4.63 4.64 4.65 4.704.67 0 50 75 33002 g06 4.62 4.68 4.69 4.66 C25 25 100 125 150 i vreg = 10ma c6 = 36v c6 = 9v temperature (c) C50 v reg (v) 4.000 4.050 150 33002 g07 3.9503.900 0 50 100 C25 25 75 125 4.1003.975 4.0253.925 4.075 c6 = 21.6v v reg rising (por) v reg falling (min sec. gate drive) temperature (c) C50 50 i vreg (ma) 51 53 54 55 6057 0 50 75 33002 g08 52 58 59 56 C25 25 100 125 150 c6 = 21.6v temperature (c) C50 1.164 v rtonp , v rtons (v) 1.176 1.188 1.200 1.212 0 50 100 150 33002 g09 1.224 1.236 C25 25 75 125 v rtonp v rtons downloaded from: http:///
ltc3300-2 7 33002f for more information www.linear.com/ltc3300-2 peak current sense threshold vs temperature zero current sense threshold vs temperature primary winding switch maximum on-time vs temperature secondary winding switch maximum on-time vs temperature maximum on-time vs r tonp , r tons watchdog timer timeout period vs temperature v rtonp , v rtons vs external resistance wdt pin current vs temperature wdt pin current vs r tons r tonp , r tons resistance (k) 1 1.164 v rtonp , v rtons (v) 1.176 1.188 1.200 1.212 1.236 10 100 33002 g10 1.224 v rtons v rtonp t a = 25c temperature (c) C50 65 i wdt (a) 70 75 80 85 C25 0 25 50 33002 g11 75 100 125 150 r tons = 15k balancing wdt = 0.5v secondary ov wdt = 2v r tons (k) 5 0 i wdt (a) 40 80 120 160 15 25 35 45 33002 g12 200 240 10 20 30 40 t a = 25c balancingwdt = 0.5v secondary ov wdt = 2v temperature (c) C50 v peak_p , v peak_s (mv) 51 53 55 25 75 150 33002 g13 49 47 45 C25 0 50 100 125 v cell = 3.6v random cell selected primary secondary temperature (c) C50 C10.0 v zero_p , v zero_s (mv) C7.5 C5.0 C2.5 0 0 50 100 150 33002 g14 2.5 5.0 C25 25 75 125 v cell = 3.6v random cell selected primary secondary temperature (c) C50 6.0 t onp(max) (s) 6.4 6.8 7.2 7.6 0 50 100 150 33002 g15 8.0 8.4 C25 25 75 125 r tonp = 20k v cell = 3.6v temperature (c) C50 1.0 t ons(max) (s) 1.1 1.2 1.3 1.4 C25 0 25 50 33002 g16 75 100 125 150 r tons = 15k r tonp , r tons (k) 5 0 t onp(max) ,t ons(max) (s) 2 6 8 10 2014 15 25 30 33002 g17 4 16 18 12 10 20 35 40 45 t a = 25c primary secondary temperature (c) C50 1.35 t wd1 (seconds) 1.40 1.45 1.50 1.55 0 50 100 150 33002 g18 1.60 1.65 C25 25 75 125 typical performance characteristics t a = 25c unless otherwise specified. downloaded from: http:///
ltc3300-2 8 33002f for more information www.linear.com/ltc3300-2 balance current vs cell voltage protection for broken connection to cell while charging protection for broken connection to secondary stack while discharging typical charge waveforms typical discharge waveforms changing balancer direction ?on the fly? balancer efficiency vs cell voltage voltage per cell (v) 2.8 89 charge transfer efficiency (%) 90 91 92 93 3.0 3.2 3.4 3.6 33002 g19 3.8 4.0 4.2 dc2064a demo boardi charge = i discharge = 2.5a for 12-cell stack only discharge, 12-cell stackdischarge, 6-cell stack charge, 6-cell stack charge, 12-cell stack voltage per cell (v) 2.8 balance current (a) 2.5 2.6 2.7 3.4 3.8 33002 g20 2.4 2.3 3.0 3.2 3.6 4.0 4.2 2.2 2.1 dc2064a demo boardi charge = i discharge = 2.5a for 12-cell stack only charge, 12-cell stack charge, 6-cell stack discharge, 12-cell stack discharge, 6-cell stack i1s 50mv/div i1p 50mv/div secondary drain 50v/div primary drain 50v/div 2s/div dc2064a demo boardi charge = 2.5a t = 2s = 12 33002 g21 i1p 50mv/div i1s 50mv/div secondary drain 50v/div primary drain 50v/div 2s/div dc2064a demo boardi discharge = 2.5a t = 2s = 12 33002 g22 c1 pin 1v/div g1p 2v/div 50s/div 33002 g23 3.6v ~5.2v connection toc1 broken balancingshuts off secondary stack voltage 10v/div g1p 2v/div 500s/div 33002 g24 43.2v ~66v connection to stack broken balancingshuts off scki 5v/div i1p 50mv/div g1p 2v/div 20s/div 33002 g25 2ms charging discharging typical performance characteristics t a = 25c unless otherwise specified. downloaded from: http:///
ltc3300-2 9 33002f for more information www.linear.com/ltc3300-2 pin functions note: the convention adopted in this data sheet is to refer to the transformer winding paralleling an individual battery cell as the primary and the transformer winding paralleling multiple series-stacked cells as the secondary, regardless of the direction of energy transfer. g6s, g5s, g4s, g3s, g2s, g1s ( pins 1, 3, 5, 7, 9, 11): g1s through g6s are gate driver outputs for driving external nmos transistors connected in series with the secondary windings of transformers whose primaries are connected in parallel with battery cells 1 through 6. for the minimum part count balancing application employing a single transformer ( ctrl = v reg ), g2s through g6s are no connects. i6s, i5s, i4s, i3s, i2s, i1s ( pins 2, 4, 6, 8, 10, 12): i1s through i6s are current sense inputs for measuring sec - ondary winding current in transformers whose primaries are connected in parallel with battery cells 1 through 6. for the minimum part count balancing application employ - ing a single transformer ( ctrl = v reg ), i2s through i6s should be tied to v C . rtons ( pin 13): secondary winding max t on setting resistor. the rtons pin servos to 1.2 v. a resistor to v C programs the maximum on-time for all external nmos transistors connected in series with secondary windings. this protects against a short-circuited current sense re - sistor in any secondary winding. to defeat this function, connect rtons to v reg . the secondary winding ovp threshold ( see wdt pin) is also slaved to the value of the r tons resistor. rtonp ( pin 14): primary winding max t on setting resistor. the rtonp pin servos to 1.2 v. a resistor to v C programs the maximum on-time for all external nmos transistors connected in series with primary windings. this protects against a short-circuited current sense resistor in any primary winding. to defeat this function, connect rtonp to v reg . ctrl : ( pin 15): control input. the ctrl pin configures the ltc3300-2 for the minimum part count application employing a single transformer if ctrl is tied to v reg or for the multiple transformer application if ctrl is tied to v C . this pin must be tied to either v reg or v C . csbi ( pin 16): chip select ( active low) input. the csbi pin interfaces to a rail-to-rail output logic gate. see serial port in the operation section. scki ( pin 17): serial clock input. the scki pin interfaces to a rail -to-rail output logic gate. see serial port in the operation section.sdi ( pin 18): serial data input. when writing data to the ltc3300-2, the sdi pin interfaces to a rail-to-rail output logic gate. see serial port in the operation section.sdo ( pin 19): serial data output. when reading data from the ltc3300-2, the sdo pin is an nmos open-drain output. see serial port in the operation section.wdt ( pin 20): watchdog timer output ( active high). at initial power-up and when not attempting to execute a valid balance command, the wdt pin is high impedance and will be pulled high ( internally clamped to ~5.6 v) if an external pull-up resistor is present. while balancing ( or attempt - ing to balance but not able to due to voltage/temperature faults) and during normal communication activity, the wdt pin is pulled low by a precision current source slaved to the r tons resistor. however, if no valid command byte is written for 1.5 seconds ( typical), the wdt output will go back high. when wdt is high, all balancers are off . the watchdog timer function can be disabled by connecting wdt to v C . the secondary winding ovp function can also be implemented using this pin (see operation section). v ? ( pin 21, exposed pad pin 49): connect v C to the most negative potential in the series of cells. the exposed pad should be connected to a continuous ( ground) plane biased at v C on the second layer of the printed circuit board by several vias directly under the ltc3300-2. i1p, i2p, i3p, i4p, i5p, i6p ( pins 22, 25, 28, 31, 34, 37): i1p through i6p are current sense inputs for measuring primary winding current in transformers connected in parallel with battery cells 1 through 6. g1p, g2p, g3p, g4p, g5p, g6p ( pins 23, 26, 29, 32, 35, 38): g1p through g6p are gate driver outputs for driving external nmos transistors connected in series with the primary windings of transformers connected in parallel with battery cells 1 through 6. downloaded from: http:///
ltc3300-2 10 33002f for more information www.linear.com/ltc3300-2 pin functions c1, c2, c3, c4, c5, c 6 ( pins 24, 27, 30, 33, 36, 39): c1 through c6 connect to the positive terminals of bat- tery cells 1 through 6. connect the negative terminal of battery cell 1 to v C . boost + ( pin 40): boost + pin. connects to the anode of the external flying capacitor used for generating sufficient gate drive necessary for balancing the topmost battery cell in a given ltc3300-2 sub-stack. a schottky diode from c6 to boost + is needed as well. alternately, the boost + pin can connect to one cell up in the above sub-stack ( if present). this pin is effectively c 7. ( note : sub - stack refers to the 3-6 battery cells connected locally to an individual ltc3300-2 as part of a larger stack.)boost ? ( pin 41): boost C pin. connects to the cathode of the external flying capacitor used for generating sufficient gate drive necessary for balancing the topmost battery cell in a given ltc3300-2 sub-stack. alternately, if the boost + pin connects to the next higher cell in the above sub-stack (if present), this pin is a no connect. boost ( pin 42): enable boost pin. connect boost to v reg to enable the boosted gate drive needed for balancing the top cell in a given ltc3300-2 sub-stack. if the boost + pin can be connected to the next cell up in the stack ( i.e., c1 of the next ltc3300-2 in the stack), then boost should be tied to v C and boost C no connected. this pin must be tied to either v reg or v C . a0, a1, a2, a3, a 4 ( pins 43, 44, 45, 46, 47): address inputs. the state of the address pins ( v reg = 1, v C = 0) determines the ltc3300-2 address. these pins must be tied to either v reg or v C . see serial port in the operation section.v reg ( pin 48): linear voltage regulator output. this 4.8 v output should be bypassed with a 1 f or larger capacitor to v C . the v reg pin is capable of supplying up to 40 ma to internal and external loads. the v reg pin does not sink current. downloaded from: http:///
ltc3300-2 11 33002f for more information www.linear.com/ltc3300-2 block diagram +C + boost + boost gate drive generator 6-cell synchronous flyback controller balancer c6 c6 c5 data 12 status 12 c5 50mv/0 0/50mv v reg v C +C 39 boost boost C v reg sd c6 40ma max v C por 4.8v 42 41 g6p 38 i6p 37 i6s 2 g6s pins 3 to 10,25 to 36 1 balancer controller +C c2 c1 v C 50mv/0 0/50mv v reg v C +C 24 g1p 23 i1p 22 i1s 12 g1s 11 20 balancer controller 2 active 2 max on-time volt-sec clamps thermal shutdown boost + 40 v C rtons 13 ctrl 15 v C wdt 16 csbi 17 scki 18 sdi 19 sdo 43 a0 45 a2 47 44 46 a4a1 a3 reset rtonp 33002 bd 14 v C 5.6v 1.2v r tons v C 21 exposed pad 49 level-shifting serial interface v reg 48 voltage regulator crc/rcrc packet error checking 16 watchdog timer 5 address downloaded from: http:///
ltc3300-2 12 33002f for more information www.linear.com/ltc3300-2 timing diagram t 6 t 7 t 3 t 5 t 4 t 1 t 8 t 2 scki sdi csbi sdo 33002 td timing diagram of the serial interface downloaded from: http:///
ltc3300-2 13 33002f for more information www.linear.com/ltc3300-2 operation battery management system (bms) the ltc3300-2 multicell battery cell balancer is a key component in a high performance battery management system ( bms) for series-connected li-ion cells. it is de - signed to operate in conjunction with a monitor, a charger, and a microprocessor or microcontroller (see figure 1). the function of the balancer is to efficiently transfer charge to/from a given out-of-balance cell in the stack from/to a larger group of neighboring cells ( which includes that individual cell) in order to bring that cell into voltage or capacity balance with its neighboring cells. ideally, this charge would always be transferred directly from/to the entire stack, but this is impractical for voltage reasons when the number of cells in the overall stack is large. the ltc3300-2 is designed to interface to a group of up to 6 series cells, so the number of ltc3300-2 ics required to balance a series stack of n cells is n/6 rounded up to the nearest integer. since the ltc3300-2 address is 5 bits, the maximum n can be is 192 cells. for connecting an individual ltc3300-2 in the stack to fewer than 6 cells, refer to the applications information section.because the balancing function entails switching large (multiampere) currents between cells, precision voltage monitoring in the bms is better served by a dedicated monitor component such as the ltc6803-2 or one of its family of parts. the ltc6803-2 provides for high precision a/d monitoring of up to 12 series cells. the only voltage monitoring provided by the ltc3300-2 is a coarse out- of-range overvoltage and undervoltage cell balancing disqualification, which provides a safety shutoff in the event kelvin sensing to the monitor component is lost. in the process of bringing the cells into balance, the over - all stack is slightly discharged. the charger component provides a means for net charging of the entire stack from an alternate power source. the last component in the bms is a microprocessor/ microcontroller which communicates directly with the balancer, monitor, and charger to receive voltage, cur - rent, and temperature information and to implement a balancing algorithm. there is no single balancing algorithm optimal for all situations. for example, during net charging of the overall stack, it may be desirable to discharge the highest voltage cells first to avoid reaching terminal charge on any cell before the entire stack is fully charged. similarly, during net discharging of the overall stack, it may be desirable to charge the lowest voltage cells first to keep them from reaching a critically low level. other algorithms may prioritize fastest time to overall balance. the ltc3300-2 implements no algorithm for balancing the stack. instead it provides maximum flexibility by imposing no limitation on the algorithm implemented as all individual cell balancers can operate simultaneously and bidirectionally. unidirectional versus bidirectional balancing most balancers in use today employ a unidirectional ( dis - charge only ) approach. the simplest of these operate by switching in a resistor across the highest voltage cell(s) in the stack ( passive balancing). no charge is recovered in this approach - instead it is dissipated as heat in the resistive element. this can be improved by employing an energy storage element ( inductive or capacitive) to transfer downloaded from: http:///
ltc3300-2 14 33002f for more information www.linear.com/ltc3300-2 cell ncell n C 1 cell n C 2 cell n C 3 cell n C 4 cell n C 5 cell n C 6 cell n C 7 cell n C 8 cell n C 9 cell n C 10 cell n C 11 cell 12 cell 11 cell 10 cell 9 cell 8 cell 7 cell 6 cell 5 cell 4 cell 3 cell 2 cell 1 c5c4 c3 c2 c1 i charge serial communication bus v C c6 c11 i load c10c9 c8 c7 c6 c5 c4 c3 c2 c1 v C c12 ltc3300-2 balancer ltc6803-2 monitor top of stack charger cn v C c5c4 c3 c2 c1 ltc3300-2 balancer v C ?? ? c6 c5c4 c3 c2 c1 v C c6 c11c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 33002 f01 v C c12 ltc3300-2 balancer ltc6803-2 monitor c5c4 c3 c2 c1 ltc3300-2 balancer v C c6 p/c v cc v ee digital isolator digital isolator digital isolator digital isolator + + + + + + + + + + + + + + + + + + + + + + + + figure 1. ltc3300-2/ltc6803-2 typical battery management system (bms) operation downloaded from: http:///
ltc3300-2 15 33002f for more information www.linear.com/ltc3300-2 operation charge from the highest voltage cell(s) in the stack to other lower voltage cells in the stack ( active balancing). this can be very efficient ( in terms of charge recovery) for the case where only a few cells in the overall stack are high, but will be very inefficient ( and time consuming) for the case where only a few cells in the overall stack are low. a bidirectional active balancing approach, such as employed by the ltc3300-2, is needed to achieve minimum balanc - ing time and maximum charge recovery for all common cell capacity errors. v cc i charge i secondary i primary v primary v secondary v top_of_stack l pri 10h g1p i1p r sns_sec 25m r sns_pri 25m g1s i1s i load (48v) (4v) t: 1 ? ? 5s single-cell discharge cycle for cell 1 single-cell charge cycle for cell 1 i peak_pri = 2a (i1p = 50mv) t i primary 5s 2a t Ci primary ~417ns 2a t Ci secondary 52v 52.05v t v primary 4v 50mv 50mv 50mv 48v 4v 48v 52v t v secondary ~417ns i peak_sec = 2a (i1s = 50mv) t i secondary 33002 f02 52v 51.95v t v primary 4v 50mv 4v 48v 50mv 50mv 52v 48v t v secondary cell 1 + cell 2 + cell 12 + cell 13 + cell n + figure 2. synchronous flyback balancing example with t = 1, s = 12 synchronous flyback balancerthe balancing architecture implemented by the ltc3300-2 is bidirectional synchronous flyback. each ltc3300-2 contains six independent synchronous flyback controllers that are capable of directly charging or discharging an individual cell. balance current is scalable with external components. each balancer operates independently of the others and provides a means for bidirectional charge transfer between an individual cell and a larger group of adjacent cells. refer to figure 2. downloaded from: http:///
ltc3300-2 16 33002f for more information www.linear.com/ltc3300-2 operation cell discharging (synchronous) when discharging is enabled for a given cell, the primary side switch is turned on and current ramps in the primary winding of the transformer until the programmed peak current ( i peak_pri ) is detected at the i n p pin. the primary side switch is then turned off, and the stored energy in the transformer is transferred to the secondary-side cells causing current to flow in the secondary winding of the transformer. the secondary - side synchronous switch is turned on to minimize power loss during the transfer period until the secondary current drops to zero ( detected at i n s). once the secondary current reaches zero, the secondary switch turns off and the primary-side switch is turned back on thus repeating the cycle. in this manner, charge is transferred from the cell being discharged to all of the cells connected between the top and bottom of the secondary sidethereby charging the adjacent cells. in the example of figure 2, the secondary-side connects across 12 cells including the cell being discharged. i peak_pri is programmed using the following equation: i peak _pri = 50mv r sns_pri cell discharge current ( primary side) and secondary-side charge recovery current are determined to first order by the following equations: i discharge = i peak _pri 2 s s + t ?? ? ?? ? i secondary = i peak _pri 2 1 s + t ?? ? ?? ? discharg e where s is the number of secondary-side cells , 1: t is the transformer turns ratio from primary to secondary, and discharge is the transfer efficiency from primary cell discharge to the secondary side stack. cell charging when charging is enabled for a given cell, the secondary- side switch for the enabled cell is turned on and current flows from the secondary - side cells through the transformer . once i peak_sec is reached in the secondary side ( detected at the i n s pin), the secondary switch is turned off and current then flows in the primary side thus charging the selected cell from the entire stack of secondary cells. as with the discharging case, the primary-side synchronous switch is turned on to minimize power loss during the cell charging phase. once the primary current drops to zero, the primary switch is turned off and the secondary - side switch is turned back on thus repeating the cycle. i peak_sec is programmed using the following equation: i peak _ sec = 50mv r sns_ sec cell charge current and corresponding secondary-side discharge current are determined to first order by the following equations: i charge = i peak _ sec 2 st s + t ?? ? ?? ? charge i secondary = i peak _ sec 2 t s + t ?? ? ?? ? where s is the number of secondary cells in the stack , 1: t is the transformer turns ratio from primary to secondary, and charge is the transfer efficiency from secondary-side stack discharge to the primary-side cell. each balancers charge transfer frequency and duty factor depend on a number of factors including i peak_pri , i peak_sec , transformer winding inductances, turns ratio, cell voltage and the number of secondary-side cells. the frequency of switching seen at the gate driver outputs is given by: f discharge = s s + t ? v cell l pri ?i peak _pri f charge = s s + t ? v cell l pri ?i peak _ sec ? t where l pri is the primary winding inductance. figure 3 shows a fully populated ltc3300-2 application employing all six balancers. downloaded from: http:///
ltc3300-2 17 33002f for more information www.linear.com/ltc3300-2 operation figure 3. ltc3300-2 6-cell active balancer module showing power connections for the multi-transformer application (ctrl = v ? ) + + + + 1:1 ? ? ?? ? ? ? ? 25m 10h cell 6 up to cell 12 cell 5cell 2 cell 1 10h c6 0.1f 10f g6p i6p g6s i6s c5 g5p i5p g5s i5s c4c3 ltc3300-2 c2 g2p i2p g2s i2s c1 g1p i1p g1s v reg boost i1s rtons rtonp boost + 6.8 boost C ctrl v C 25m 1:1 25m 10h 10h 25m 1:1 25m 10h 10h 25m 1:1 25m 10h 10h 25m 6.98k 33002 f03 22.6k 10f ?? ? ?? ? ? ? 10f ? ? 10f ? ? 10f serial communication related pins a4a3 a2 a1 a0 csbi scki sdi sdo wdt downloaded from: http:///
ltc3300-2 18 33002f for more information www.linear.com/ltc3300-2 balancing high voltage battery stacks balancing series connected batteries which contain >>12 cells in series requires interleaving of the transformer sec- ondary connections in order to achieve full stack balancing while limiting the breakdown voltage requirements of the primary- and secondary-side power fets. figure 4 shows typical interleaved transformer connections for a multicell battery stack in the generic sense, and figure 5 for the specific case of an 18- cell stack. in these examples, the secondary side of each transformer is connected to the top of the cell that is 12 positions higher in the stack than the bottom of the lowest voltage cell in each ltc3300-2 sub-stack. for the top most ltc3300-2 in the stack, it is not possible to connect the secondary side of the trans- former across 12 cells. instead, it is connected to the top of the stack, or effectively across only 6 cells. interleaving in this fashion allows charge to transfer between 6- cell sub-stacks throughout the entire battery stack. max on-time volt-sec clamps the ltc3300-2 contains programmable fault protection clamps which limit the amount of time that current is allowed to ramp in either the primary or secondary wind - ings in the event of a shorted sense resistor. maximum on time for all primary connections ( active during cell discharging) and all secondary connections ( active during cell charging) is individually programmable by connecting resistors from the r tonp and r tons pins to v C according to the following equations: t on(max)|primary = 7.2s r tonp 20k t on(max)|secondary = 1.2s r tons 15k for more information on selecting the appropriate maximum on-times, refer to the applications information section.to defeat this function, short the appropriate r ton pin(s) to v reg . operation figure 4. diagram of power transfer interleaving through the stack, transformer connections for high voltage stacks + + ?? ? ? ltc3300-2 power stages ltc3300-2 power stages from cell n-12 secondary to cell 24 pri sec + + + + + + ? ? ? ? ? ? ? ? ? ? ? ? ltc3300-2 power stages ?? ? ?? ? ?? ? ?? ? sec pri sec pri + + ? ? ? ? cell 18cell 13 cell 6 cell 7 cell 12 cell n-6 cell n cell 1 cell 2 cell 3 cell 4 cell 5 33002 f04 ltc3300-2 power stages pri top sec + + ? ? ? ? downloaded from: http:///
ltc3300-2 19 33002f for more information www.linear.com/ltc3300-2 operation figure 5. 18-cell active balancer showing power connections, interleaved transformer secondaries and boost + rail generation up the stack 1:1 10h to transformer secondaries of balancers 14 to 18 10h cell 18 25m 25m c1 c6 g1p i1p g1s i1s v reg v C ltc3300-2 boost boost + boost C 0.1f 6.8 1:1 10h to transformer secondaries of balancers 8 to 12 10h 25m 25m c1 c6 g1p i1p g1s i1s v C ltc3300-2 boost boost + 1:1 10h to transformer secondaries of balancers 2 to 6 10h 25m 25m 33002 f05 c1 c6 g1p i1p g1s i1s v C ltc3300-2 boost boost + + cell 13 + cell 12 + cell 7 + cell 6 + cell 1 + ? ? 10f ? ? 10f ? ? 10f downloaded from: http:///
ltc3300-2 20 33002f for more information www.linear.com/ltc3300-2 operation gate drivers/gate drive comparators all secondary-side gate drivers ( g1s through g6s) are powered from the v reg output, pulling up to 4.8 v when on and pulling down to v C when off. all primary-side gate drivers ( g1p through g6p) are powered from their respective cell voltage and the next cell voltage higher in the stack ( see table 1). an individual cell balancer will only be enabled if its corresponding cell voltage is greater than 2v and the cell voltage of the next higher cell in the stack is also greater than 2 v. for the g6p gate driver output, the next higher cell in the stack is c1 of the next higher ltc3300-2 in the stack ( if present) and is only used if the boosted gate drive is disabled ( by connecting boost = v C ). if the boosted gate drive is enabled ( by connecting boost = v reg ), only the c6 cell voltage is looked at to enable balancing of cell 6. in the case of the topmost ltc3300-2 in the stack, the boosted gate drive must be enabled. the boosted gate drive requires an external diode from c6 to boost + and a boost capacitor from boost + to boost C . for information on selecting these components, refer to the applications information section. also note that the dynamic supply current referred to in note 4 of the electrical characteristics table adds to the terminal currents of the pins indicated in the voltage when off and voltage when on columns of table 1. the gate drive comparators have a dc hysteresis of 70 mv. for improved noise immunity, the inputs are internally low pass filtered and the outputs are filtered so as to not transition unless the internal comparator state is unchanged for 3 s to 6 s ( typical). if insufficient gate drive is detected while active balancing is in progress ( perhaps, for example, if the stack is under heavy load), the affected balancer(s) and only the affected balancer(s) will shut off. the balance command remains stored in memory, and active balancing will resume where it left off if sufficient gate drive is subsequently restored. this can happen if, for example, the stack is being charged. cell overvoltage comparators in addition to sufficient gate drive being required to en - able balancing , there are additional comparators which disable all active balancing if any of the six individual cell voltages is greater than 5 v. these comparators have a dc hysteresis of 500 mv. for improved noise immunity, the inputs are internally low pass filtered and the outputs are filtered so as to not transition unless the internal comparator state is unchanged for 3 s to 6 s ( typical). if any cell voltage goes overvoltage while active balanc - ing is in progress, all active balancers will shut off. the balance command remains stored in memory, and active balancing will resume where if left off if the cell voltage subsequently comes back in range. these comparators will protect the ltc3300-2 if a connection to a battery is lost while balancing and the cell voltage is still increasing as a result of that balancing. voltage regulator a linear voltage regulator powered from c6 creates a 4.8v rail at the v reg pin which is used for powering certain internal circuitry of the ltc3300-2 including all 6 secondary gate drivers. the v reg output can also be used for powering external loads, provided that the total dc loading of the regulator does not exceed 40 ma at which point current limit is imposed to limit on-chip power dis - table 1 driver output voltage when off voltage when on gate drive required to enable balancing g1p v- c2 (c2 C c1) 2v and (c1 C v C ) 2v g2p c1 c3 (c3 C c2) 2v and (c2 C c1) 2v g3p c2 c4 (c4 C c3) 2v and (c3 C c2) 2v g4p c3 c5 (c5 C c4) 2v and (c4 C c3) 2v g5p c4 c6 (c6 C c5) 2v and (c5 C c4) 2v g6p c5 if boost = v reg : boost+ (generated) (c6 C c5) 2v if boost = v C : boost + = c7* (c7* C c6) 2v and (c6 C c5) 2v *c7 is equal to c1 of the next higher ltc3300-2 in the stack if this connection is used. downloaded from: http:///
ltc3300-2 21 33002f for more information www.linear.com/ltc3300-2 sipation. the internal component of the dc load current is dominated by the average gate driver current(s ) ( g1s through g6s), each approximated by c ? v ? f, where c is the gate capacitance of the external nmos transistor, v = v reg = 4.8 v, and f is the frequency that the gate driver output is running at. fet manufacturers usually specify the c ? v product as q g ( gate charge) measured in coulombs at a given gate drive voltage. the frequency, f , is dependent on many terms, primarily the voltage of each individual cell, the number of cells in the secondary stack, the programmed peak balancing current, and the transformer primary and secondary winding inductances. in a typical application, the c ? v ? f current loading the v reg output is expected to be low single - digit milliamperes per driver. note that the v reg loading current is ultimately delivered from the c6 pin. for applications involving very large balance currents and/or employing external nmos transistors with very large gate capacitance, the v reg output may need to source more than 40 ma average. for information on how to design for these situations, refer to the applications information section. one additional function slaved to the v reg output is the power-on reset ( por). during initial power-up and subsequently if the v reg pin voltage ever falls below ap- proximately 4 v ( e.g., due to overloading), the serial port is cleared to the default power-up state with no balancers active. this feature thus guarantees that the minimum gate drive provided to the external secondary side fets is also 4v. for a 10 f capacitor loading the output at initial power- up, the output reaches regulation in approximately 1ms.thermal shutdown the ltc3300-2 has an overtemperature protection circuit which shuts down all active balancing if the internal silicon die temperature rises to approximately 155 c. when in thermal shutdown, all serial communication remains active and the cell balancer status ( which contains temperature information) can be read back. the balance command which had been being executed remains stored in memory . this function has 10 c of hysteresis so that when the die temperature subsequently falls to approximately 145 c, active balancing will resume with the previously execut - ing command. w atchdog t imer circuit the watchdog timer circuit provides a means of shutting down all active balancing in the event that communication to the ltc3300-2 is lost. the watchdog timer initiates when a balance command begins executing and is reset to zero every time a valid 8- bit command byte ( see serial port operation) is written. the valid command byte can be an execute, a write, or a read ( command or status). partial reads and writes are considered valid, i.e., it is only necessary that the first 8 bits have to be written and contain the correct address. referring to figure 6 a, at initial power-up and when not balancing, the wdt pin is high impedance and will be pulled high ( internally clamped to ~5.6 v) if an external pull-up resistor is present. while balancing and during normal communication activity, the wdt pin is pulled low by a precision current source equal to 1.2 v/r tons . (note: if the secondary volt-second clamp is defeated by connecting r tons to v reg , the watchdog function is also defeated.) if no valid command byte is written for 1.5 seconds (typical), the wdt output will go back high. when wdt is high, all balancers will be shut down but the previously executing balance command still remains in memory. from this timed-out state, a subsequent valid command byte will reset the timer, but the balancers will only restart if an execute command is written. to defeat the watchdog function, simply connect the wdt pin to v C . pause/resume balancing (via wdt pin) the wdt output pin doubles as a logic input ( ttl levels) which can be driven by an external logic gate as shown in figure 6 b ( no watchdog), or by a pmos/three-state logic gate as shown in figure 6 c ( with watchdog) to pause and resume balancing in progress. the external pull-up must have sufficient drive capability to override the current source to ground at the wdt pin (= 1.2 v/r tons ). provided that the internal watchdog timer has not independently timed out, externally pulling the wdt pin high will immediately pause balancing, and it will resume where it left off when the pin is released. operation downloaded from: http:///
ltc3300-2 22 33002f for more information www.linear.com/ltc3300-2 operation active 5.6v ltc3300-2 v reg wdt rtons r tons 33002 f06a v C 1.2v r tons r wdt active 5.6v ltc3300-2 v th = 1.4v v reg wdt rtons r tons pause/ resume 33002 f06b 1.2v r tons active 5.6v v reg v reg to transformer secondary windings ltc3300-2 wdt rtons r tons v reg v reg pause/ resume either/or pause/ resume 33002 f06c 1.2v r tons r sec_ovp (6a) watchdog timer only (wdt = v ? to defeat) (6b) pause/resume balancing only (6c) watchdog timer with pause/resume balancing and secondary winding ovp protection figure 6. wdt pin connection options secondary winding ovp function (via wdt pin) the precision current source pull-down on the wdt pin during balancing can be used to construct an accurate secondary winding ovp protection circuit as shown in figure 6 c. a second external resistor, scaled to r tons and connected to the transformer secondary winding, is used to set the comparator threshold. an nmos cascode device ( with gate tied to v reg ) is also needed to protect the wdt pin from high voltage. the secondary winding ovp thresholds are given by: v sec|ovp(rising) = 1.4v + 1.2v ? (r sec_ovp /r tons ) v sec|ovp(falling) = 1.4v + 1.05v ? (r sec_ovp /r tons ) this comparator will protect the ltc3300-2 application circuit if the secondary winding connection to the battery stack is lost while balancing and the secondary winding voltage is still increasing as a result of that balancing. the balance command remains stored in memory, and active balancing will resume where it left off if the stack voltage subsequently falls to a safer level.single transformer application (ctrl = v reg ) figure 7 shows a fully populated ltc3300-2 application employing all six balancers with a single shared custom transformer. in this application, the transformer has six primary windings coupled to a single secondary winding. only one balancer can be active at a given time as all six share the secondary gate driver g1s and secondary current sense input i1s. the unused gate driver outputs g2s-g6s must be left floating and the unused current sense inputs i2s-i6s should be connected to v C . any balance command which attempts to operate more than one balancer at a time will be ignored. this application represents the minimum component count active balancer achievable. downloaded from: http:///
ltc3300-2 23 33002f for more information www.linear.com/ltc3300-2 operation figure 7. ltc3300-2 6-cell active balancer module showing power connections for the single transformer application (ctrl = v reg ) 10h each 1:1 ? up to cell 12 ?? ? 25m cell 6 + 10h 25m cell 5 + 10h10h 10h 10h ? ? ? ? ? ? 25m cell 4 + 25m cell 3 + 25m cell 2 + 25m cell 1 nc 33002 f07 6.98k + 25m 22.6k 10f boost + c6 g6p i6p c5 g5p i5p c4 g4p i4p c3 g3p i3p c2 g2p ltc3300-2 i2p c1 g1pg1s i1s g2s-g6s i2s-i6s v C ctrl boost v reg 10f i1p boost C rtons rtonp 0.1f 6.8 serial communication related pins 10f 10f 10f 10f 10f a4a3 a2 a1 a0 csbi scki sdi sdo wdt downloaded from: http:///
ltc3300-2 24 33002f for more information www.linear.com/ltc3300-2 csbiscki sdi msb (cmd) lsb (cmd) 33002 f08 csbiscki sdi msb (cmd) lsb (cmd) lsb (data) msb (data) (8a) transmission format (write) (8b) transmission format (read) lsb (data) msb (data) sdo figure 8. operation serial port operation overview the ltc3300-2 has an spi bus compatible serial port. devices can be connected in parallel, using digital isolators . multiple devices are uniquely identified by a part address determined by the a0 to a4 pins.physical layer on the ltc3300-2, four pins comprise the serial interface : csbi, scki, sdi and sdo. the sdo and sdi pins may be tied together, if desired, to form a single bidirectional port. five address pins ( a0 to a4) set the part address. all serial communication related pins are voltage mode with voltage levels referenced to the v reg and v C supplies. data link layer clock phase and polarity: the ltc3300-2 spi-compatible interface is configured to operate in a system using cpha = 1 and cpol = 1. consequently, data on sdi must be stable during the rising edge of scki. data transfers: every byte consists of 8 bits. bytes are transferred with the most significant bit ( msb) first. on a write, the data value on sdi is latched into the device on the rising edge of scki ( figure 8 a). similarly, on a read, the data value on sdo is valid during the rising edge of scki and transitions on the falling edge of scki ( figure 8 b ). csbi must remain low for the entire duration of a com- mand sequence , including between a command byte and subsequent data. on a write command, data is latched in on the rising edge of csbi. downloaded from: http:///
ltc3300-2 25 33002f for more information www.linear.com/ltc3300-2 operation command byteall communication to the ltc3300-2 takes place with csbi logic low. the first 8 clocked in data bits after a high-to- low transition on csbi represent the command byte. the 8-bit command byte is written msb first per table 2. the first 5 bits must match the fixed pin-strapped address [a4 a3 a2 a1 a0] for the individual device, or all sub- sequent data will be ignored until csbi transitions high and then low again. the 6 th and 7 th bits program one of four commands as shown in table 3. the 8 th bit in the command byte must be set such that the entire 8- bit com - mand byte has even parity. if the parity is incorrect, the current balance command being executed ( from the last previously successful write) is terminated immediately and all subsequent ( write) data is ignored until csbi transi - tions high and then low again. incorrect parity takes this action whether or not the address matches. this thereby provides a fast means to immediately terminate balancing - in-progress by intentionally writing a command byte with incorrect parity. table 2. command byte bit mapping (defaults to 0x00 in reset state) a4 (msb) a3 a2 a1 a0 cmda cmdb parity bit (lsb) table 3. command bits cmda cmdb communication action 0 0 write balance command (without executing) 0 1 readback balance command 1 0 read balance status 1 1 execute balance command write balance command if the command bits program write balance command, all subsequent write data must be exactly 16 bits ( before csbi transitions high) or it will be ignored. the internal command holding register will be cleared which can be verified on readback. the current balance command being executed ( from the last previously successful write) will continue, but all active balancing will be turned off if an execute balance command is subsequently written. only the individual ltc3300-2 in the stack with the matching address will load in the write data. the 16- bit write balance command is written msb first per table 4. the first 12 bits of the 16- bit balance command are used to indicate which balancer ( or balancers) is active and in which direction ( charge or discharge). each of the 6 cell balancers is controlled by 2 bits of this data per table 5. the balancing algorithm for a given cell is: charge cell n : ramp up to i peak in secondary winding, ramp down to i zero in primary winding. repeat. discharge cell n ( synchronous): ramp up to ipeak in primary winding, ramp down to i zero in secondary winding. repeat. table 5. cell balancer control bits d n a d n b balancing action ( n = 1 to 6) 0 0 none 0 1 discharge cell n (nonsynchronous) 1 0 discharge cell n (synchronous) 1 1 charge cell n table 4. write balance command data bit mapping (defaults to 0x000f in reset state) d1a (msb) d1b d2a d2b d3a d3b d4a d4b d5a d5b d6a d6b crc[3] crc[2] crc[1] crc[0] (lsb) downloaded from: http:///
ltc3300-2 26 33002f for more information www.linear.com/ltc3300-2 operation for nonsynchronous discharging of cell n , both the sec- ondary winding gate drive and ( zero) current sense amp are disabled. the secondary current will conduct either through the body diode of the secondary switch ( if pres - ent) or through a substitute schottky diode. the primary will only turn on again after the secondary winding volt- sec clamp times out. in a bidirectional application with a secondary switch, it may be possible to achieve slightly higher discharge efficiency by opting for nonsynchronous discharge mode ( if the gate charge savings exceed the added diode drop losses) but the balancing current will be less predictable because the secondary winding volt-sec clamp must be set longer than the expected time for the current to hit zero in order to guarantee no current rever - sal . in the case where a schottky diode replaces the sec- ondar y switch, it is possible to build a undirectional discharge-only balancing application charging an isolated auxiliary cell as shown in figure 16 in the typical applica - tions section. in the ctrl = 1 application of figure 7 employing a single transformer which can only balance one cell at a time, any command requesting simultaneous balancing of more than one cell will be ignored. all active balancing will be turned off if an execute balance command is subse- quently written. the last 4 bits of the 16- bit balance command are used for packet error checking ( pec). the 16 bits of write data (12-bit message plus 4- bit crc) are input to a cyclic re - dundancy check ( crc) block employing the international telecommunication union crc-4 standard characteristic polynomial: x 4 + x + 1 in the write data, the 4- bit crc appended to the message must be selected such that the remainder of the crc divi - sion is zero. note that the crc bits in the write balance command are inverted. this was done so that an all zeros command is invalid. the ltc3300-2 will ignore the write data if the remainder is not zero and the internal command holding register will be cleared which can be verified on readback. the current balance command being executed (from the last previously successful write) will continue, but all active balancing will be turned off if an execute bal - ance command is subsequently written. for information on how to calculate the crc including an example, refer to the applications information section.readback balance command the bit mapping for readback balance command is identi- cal to that for write balance command. if the command bits program readback balance command, the 16 bits of previously written data ( latched in 12- bit message plus newly calculated 4- bit crc) are shifted out in the same order bitwise ( msb first) per table 4. only the individ- ual ltc3300-2 in the stack with the matching address will send out the read data. this command allows for microprocessor verification of written commands before executing. note that the crc bits in the readback balance command are also inverted . this was done so that an all zeros readback is invalid.read balance status if the command bits program read balance status , 16 bits of status data (12 bits of data plus associated 4- bit crc) are shifted out msb first per table 6. similar to a readback balance command, the last 4 bits in each 16- bit balance status are used for error detection. the first 12 bits of the status are input to a cyclic redundancy check ( crc) block employing the same characteristic polynomial used for write commands. the ltc3300-2 will calculate and append the appropriate 4- bit crc to the outgoing 12- bit message which can then be used for microprocessor er - table 6. read balance status data bit mapping (defaults to 0x000f in reset state) gate drive 1 ok (msb) gate drive 2 ok gate drive 3 ok gate drive 4 ok gate drive 5 ok gate drive 6 ok cells not ov sec not ov temp ok 0 0 0 crc[3] crc[2] crc[1] crc[0] (lsb) downloaded from: http:///
ltc3300-2 27 33002f for more information www.linear.com/ltc3300-2 operation ror checking. only the individual ltc3300-2 in the stack with the matching address will send out the status data. note that the crc bits in the read balance status are inverted. this was done so that an all zeros readback is invalid. the first 6 bits of the read balance status indicate if there is sufficient gate drive for each of the 6 balancers. these bits correspond to the right-most column in table 1, but can only be logic high for a given balancer following an execute command involving that same balancer. if a bal - ancer is not active, its gate drive ok bit will be logic low. the 7 th , 8 th, and 9 th bits in the read balance status indicate that all 6 cells are not overvoltage, that the transformer secondary is not overvoltage, and that the ltc3300-2 die is not overtemperature, respectively. these 3 bits can only be logic high following an execute command involving at least one balancer. the 10 th , 11 th, and 12 th bits in the read balance status are currently not used and will always be logic zero. as an example, if balancers 1 and 4 are both active with no voltage or temperature faults, the 12- bit read balance status should be 100100111000. execute balance commandif the command bits program execute balance command, the last successfully written and latched in balance com- mand will be executed immediately. all subsequent ( write) data will be ignored until csbi transitions high and then low again.pause/resume balancing (via spi port) the ltc3300-2 provides a simple means to interrupt bal - ancing in progress ( stack wide) and then restart without having to rewrite the previous balance command to all ltc3300-2 ics in the stack. to pause balancing, simply write an 8- bit execute balance command with incorrect parity. to resume balancing, simply write an execute bal - ance command with the correct parity to each different address. this feature is useful if precision cell voltage measurements want to be performed during balancing with the stack quiet. immediate pausing of balancing in progress will occur for any 8- bit command byte with incorrect parity. the restart time is typically 2 ms which is the same as the delayed start time after a new or different balance command (t dly_start ). it is measured from the 8 th rising scki edge until the balancer turns on and is illustrated in g25 in the typical performance characteristics section. downloaded from: http:///
ltc3300-2 28 33002f for more information www.linear.com/ltc3300-2 applications information external sense resistor selection the external current sense resistors for both primary and secondary windings set the peak balancing current according to the following formulas: r sense|primary = 50mv i peak _pri r sense|secondary = 50mv i peak _ sec balancer synchronization due to the stacked configuration of the individual synchro- nous flyback power circuits and the interleaved nature of the gate drivers, it is possible at higher balance currents for adjacent and/or penadjacent balancers within a group of six to sync up. the synchronization will typically be to the highest frequency of any active individual balancer and can result in a slightly lower balance current in the other affected balancer(s). this error will typically be very small provided that the individual cells are not significantly out of balance voltage-wise and due to the matched i peak / i zero s and matched power circuits. balancer synchro- nization can be reduced by lowpass filtering the primary and/or secondary current sense signals with a simple rc network as shown in figure 9. a good starting point for the rc time constant is one-tenth of the on-time of the associated switch ( primary or secondary). in the case of i peak sensing, phase lag associated with the lowpass filter will result in a slightly lower voltage seen by the ltc3300-2 compared to the true sense resistor voltage. this error can be compensated for by selecting the r value to add back this same drop using the typical current value of 20 a out of the ltc3300-2 current sense pins at the comparator trip point. setting appropriate max on-times the primary and secondary winding volt-second clamps are intended to be used as a current runaway protection feature and not as a substitute means of current control replacing the sense resistors. in order to not interfere with normal i peak /i zero operation, the maximum on times must be set longer than the time required to ramp to i peak ( or i zero ) for the minimum cell voltage seen in the application: t on(max)|primary > l pri ? i peak_pri /v cell(min) t on ( max)|secondary > l pri ? i peak _ sec ? t /( s ? v cell ( min ) ) these can be further increased by 20% to account for manufacturing tolerance in the transformer winding inductance and by 10% to account for i peak variation. external fet selection in addition to being rated to handle the peak balancing current, external nmos transistors for both primary and secondary windings must be rated with a drain-to-source breakdown such that for the primary mosfet: v ds(breakdown)|min > v cell + v stack + v diode t = v cell 1 + s t ?? ? ?? ? + v diode t and for the secondary mosfet: v ds(breakdown)|min > v stack + t v cell + v diode ( ) = v cell s + t ( ) + t v diode where s is the number of cells in the secondary winding stack and 1: t is the transformer turns ratio from primary to secondary. for example, if there are 12 li-ion cells in the secondary stack and using a turns ratio of 1:2, the primary fets would have to be rated for greater than 4.2 v (1 + 6) + 0.5 = 29.9 v and the secondary fets would have to be rated for greater than 4.2v (12 + 2) + 2v = 60.8v. ltc3300-2 n = 2 to 6 20a r c r sns 33002 f09 g1p/g n p/g1s/g n s i1p/i n p/i1s/i n s v C /c n C 1/v C /v C figure 9. using an rc network to filter current sense inputs to the lt c 3300-2 downloaded from: http:///
ltc3300-2 29 33002f for more information www.linear.com/ltc3300-2 applications information good design practice recommends increasing this voltage rating by at least 20% to account for higher voltages present due to leakage inductance ringing. see table 7 for a list of fets that are recommended for use with the ltc3300-2. table 7 part number manufacturer i ds(max) v ds(max) sir882dp vishay 60a 100v sis892dn vishay 25a 100v ipd70n10s3-12 infineon 70a 100v ipb35n10s3l-26 infineon 35a 100v rjk1051dpb renesas 60a 100v rjk1054dpb renesas 92a 100v transformer selection the ltc3300-2 is optimized to work with simple 2- wind- ing transformers with a primary winding inductance of between 1 and 20 microhenries, a 1:2 turns ratio ( primary to secondary), and the secondary winding paralleling up to 12 cells. if a larger number of cells in the secondary stack is desired for more efficient balancing, a transformer with a higher turns ratio can be selected. for example, a 1:10 transformer would be optimized for up to 60 cells in the secondary stack. in this case the external fets would need to be rated for a higher voltage ( see above). in all cases the saturation current of the transformer must be selected to be higher than the peak currents seen in the application.see table 8 for a list of transformers that are recommended for use with the ltc3300-2. table 8 part number manufacturer turns ratio* primary inductance i s at 750312504 (smt) wrth electronics 1:1 3.5h 10a 750312677 (tht) wrth electronics 1:1 3.5h 10a ma5421-al coilcraft 1:1 3.4h 10a ctx02-18892-r coiltronics 1:1 3.4h 10a xf0036-ep13s xfmrs inc 1:1 3h 10a loo-3218 bh electronics 1:1 3.4h 10a dhcp-x79-1001 toko 1:1 3.4h 10a c128057lf gci 1:1 3.4h 10a t10857-1 inter tech 1:1 3.4h 10a *all transformers listed in the table are 8-pin components and can be configured with turns ratios of 1:1, 1:2, 2:1, or 2:2. snubber design careful attention must be paid to any transient ringing seen at the drain voltages of the primary and secondary winding fets in application. the peak of the ringing should not approach and must not exceed the breakdown voltage rating of the fets chosen. minimizing leakage inductance present in the application and utilizing good board layout techniques can help mitigate the amount of ringing. in some applications, it may be necessary to place a series resistor + capacitor snubber network in parallel with each winding of the transformer. this network will typically lower efficiency by a few percent, but will keep the fets in a safer operating region. determining values for r and c usually requires some trial-and-error optimization in the application. for the transformers shown in table 8, good starting point values for the snubber network are 330 in series with 100pf.boosted gate drive component selection (boost = v reg ) the external boost capacitor connected from boost + to boost C supplies the gate drive voltage required for turning on the external nmos connected to g6p. this capacitor is charged through the external schottky diode from c6 to boost + when the nmos is off ( g6p = boost C = c5). when the nmos is to be turned on, the boost C driver switches the lower plate of the capacitor from c5 to c6, and the boost + voltage common modes up to one cell voltage higher than c6. when the nmos turns off again, the boost C driver switches the lower plate of the capaci- tor back to c5 so that the boost capacitor is refreshed.a good rule of thumb is to make the value of the boost capacitor 100 times that of the input capacitance of the nmos at g6p . for most applications, a 0.1 f /10 v capacitor will suffice. the reverse breakdown of the schottky diode must only be greater than 6 v. to prevent an excessive and potentially damaging surge current from flowing in the boosted gate drive components during initial connection of the battery voltages to the ltc3300-2, it is recommended to place a 6.8 resistor in series with the schottky diode as shown in figure 3. the surge current must be limited to 1a to avoid potential damage. downloaded from: http:///
ltc3300-2 30 33002f for more information www.linear.com/ltc3300-2 applications information sizing the cell bypass caps for broken connection protection if a single connection to the battery stack is lost while bal - ancing, the differential cell voltages seen by the ltc3300-2 power circuit on each side of the break can increase or decrease depending on whether charging or discharging and where the actual break occurred. the worst-case scenario is when the balancers on each side of the break are both active and balancing in opposite directions. in this scenario, the differential cell voltage will increase rapidly on one side of the break and decrease rapidly on the other. the cell overvoltage comparators working in conjunction with appropriately-sized differential cell bypass capacitors protect the ltc3300-2 and its asso- ciated power components by shutting off all balancing before any local differential cell voltage reaches its abso- lute maximum rating. the comparator threshold ( rising) is 5 v, and it takes 3 s to 6 s for the balancing to stop, during which the bypass capacitor must prevent the dif - ferential cell voltage from increasing past 6 v. therefore, the minimum differential bypass capacitor value for full broken connection protection is: c bypass(min) = i charge + i discharge ( ) ? 6s 6v C 5v if i charge and i discharge are set nominally equal, then approximately 12 f of real capacitance per amp of balance current is required. protection from a broken connection to a cluster of sec - ondary windings is provided local to each ltc3300-2 in the stack by the secondary winding ovp function ( via wdt pin) described in the operation section. however, because of the interleaving of the transformer windings up the stack, it is possible for a remote ltc3300-2 to still act on the cell voltage seen locally by another ltc3300-2 at the point of the break which has shut itself off. for this reason, each cluster of secondary windings must have a dedicated connection to the stack separate from the individual cell connection that it connects to.using the ltc3300-2 with fewer than 6 cells to balance a series stack of n cells, the required number of ltc3300-2 ics is n/6 rounded up to the nearest integer. since the ltc3300-2 address is 5 bits, the maximum n can be is 192 cells. additionally, each ltc3300-2 in the stack must interface to a minimum of 3 cells ( must include c4, c5, and c6). thus, any stack of between 3 and 192 cells can be balanced using an appropriate stack of ltc3300-2 ics. unused cell inputs ( c1, c 1 + c2, or c 1 + c 2 + c3) in a given ltc3300-2 sub-stack should be shorted to v C ( see figure 10). however, in all configurations, the write data remains at 16 bits. the ltc3300-2 will not act on the cell balancing bits for the unused cell(s) but these bits are still included in the crc calculation. figure 10. battery stack connections for 5, 4 or 3 cells + cell n + 4 ?? ? ? ? ? + cell n + 3 + cell n + 2 + cell n + 1 + cell n c6 ltc3300-2 (10a) sub-stack using only 5 cells (10b) sub-stack using only 4 cells (10c) sub-stack using only 3 cells v C c5c4 c3 c2 c1 + ?? ? ? ? ? + cell n + 3 + cell n + 2 + cell n + 1cell n c6 ltc3300-2 v C c5c4 c3 c2 c1 + ?? ? ? ? ? + + cell n + 2 cell n + 1cell n 33002 f10 c6 ltc3300-2 v C c5c4 c3 c2 c1 downloaded from: http:///
ltc3300-2 31 33002f for more information www.linear.com/ltc3300-2 applications information figure 11. adding external buck dc/dc for >40ma v reg drive 4.8v linear voltage regulator v reg c out r fb2 v C ltc3300-2 c6 5v i out > 40ma l r fb1 c in 33002 f11 sw gnd v in buck dc/dc fb supplementary voltage regulator drive (>40ma) the 4.8 v linear voltage regulator internal to the ltc3300-2 is capable of providing 40 ma at the v reg pin. if additional current capability is required, the v reg pin can be back- driven by an external low cost 5 v buck dc/dc regulator powered from c6 as shown in figure 11. the internal regulator of the ltc3300-2 has very limited sink current capability and will not fight the higher forced voltage. fault protection care should always be taken when using high energy sources such as batteries. there are numerous ways that systems can be misconfigured when considering the assembly and service procedures that might affect a battery system during its useful lifespan. table 9 shows the various situations that should be considered when planning protection circuitry. the first four scenarios are to be anticipated during production and appropriate protection is included within the ltc3300-2 device itself. table 9. ltc3300-2 failure mechanism effect analysis scenario effect design mitigation top cell (c6) input connection loss to ltc3300-2. power will come from highest connected cell input or via data port fault current. clamp diodes at each pin to c6 and v C (within ic) provide alternate power path. diode conduction at data ports will impair communication with higher potential units. bottom cell (v C ) input connection loss to ltc3300-2. power will come from lowest connected cell input or via data port fault current. clamp diodes at each pin to c6 and v C (within ic) provide alternate power path. diode conduction at data ports will impair communication with higher potential units. random cell (c1-c5) input connection loss to ltc3300-2. power-up sequence at ic inputs/differential input voltage overstress. clamp diodes at each pin to c6 and v C (within ic) provide alternate power path. zener diodes across each cell voltage input pair (within ic) limit stress. disconnection of a harness between a sub-stack of battery cells and the ltc3300-2 (in a system of stacked groups). loss of all supply connections to the ic. clamp diodes at each pin to c6 and v C (within ic) provide alternate power path if there are other devices (which can supply power) connected to the ltc3300-2. secondar y winding connection loss to battery stack. secondary winding power fet could be subjected to a higher voltage as bypass capacitor charges up. wdt pin implements a secondary winding ovp circuit which will detect overvoltage and terminate balancing. shorted primary winding sense resistor. primary winding peak current cannot be detected to shut off primary switch. maximum on-time set by r tonp resistor will shut off primary switch if peak current detect doesnt occur. shorted secondary winding sense resistor. secondary winding peak current cannot be detected to shut off secondary switch. maximum on-time set by r tons resistor will shut off secondary switch if peak current detect doesnt occur. data error (noise margin induced or otherwise) occurs during a write command. incoming checksum will not agree with the incoming message when read in by any individual ltc3300-2 in the stack. since the crc remainder will not be zero, the ltc3300-2 will not execute the write command, even if an execute command is given. all balancers with nonzero remainders will be off. data error (noise margin induced or otherwise) occurs during a read command. outgoing checksum (calculated by the ltc3300 -2) will not agree with the outgoing message when read in by the host microprocessor. since the crc remainder (calculated by the host) will not be zero, the data cannot be trusted. all balancers will remain in the state of the last previously successful write. downloaded from: http:///
ltc3300-2 32 33002f for more information www.linear.com/ltc3300-2 applications information internal protection diodes each pin of the ltc3300-2 has protection diodes to help prevent damage to the internal device structures caused by external application of voltages beyond the supply rails as shown in figure 12. the diodes shown are conventional silicon diodes with a forward breakdown voltage of 0.5 v. the unlabeled zener diode structures have a reverse- breakdown characteristic which initially breaks down at 9v then snaps back to a 7 v clamping potential. the zener diodes labeled z clamp are higher voltage devices with an initial reverse breakdown of 25 v snapping back to 22 v. the forward voltage drop of all zeners is 0.5v. the internal protection diodes shown in figure 12 are power devices which are intended to protect against limited-power transient voltage excursions. given that these voltages exceed the absolute maximum ratings of the ltc3300-2, any sustained operation at these voltage levels will damage the ic. initial battery connection to ltc3300-2 in addition to the above-mentioned internal protection diodes, there are additional lower voltage/lower current diodes across each of the six differential cell inputs ( not shown in figure 12) which protect the ltc3300-2 during initial installation of the battery voltages in the application. these diodes have a breakdown voltage of 5.3 v with 20 k of series resistance and keep the differential cell voltages below their absolute maximum rating during power-up when the cell terminal currents are zero to tens of mi - croamps. this allows the six batteries to be connected in any random sequence without fear of an unconnected cell input pin overvoltaging due to leakage currents acting on its high impedance input. differential cell-to-cell bypass capacitors used in the application must be of the same nominal value for full random sequence protection. analysis of stack terminal currents in shutdown as given in the electrical characteristics table, the quiescent current of the ltc3300-2 when not balancing is 14 a at the c6 pin and zero at the c1 through c5 pins. all of this 14a shows up at the v C pin of the ltc3300-2. to the extent that the 14 a currents match perfectly chip-to-chip in a long series stack, the resultant stack terminal currents in shutdown are as follows : 14 a out of the top of stack node and 14 a into the bottom of stack node. all other intermediate node currents are zero. differences between ltc3300-2 and ltc3300-1 the ltc3300-1 employs an spi - compatible serial interface in which each ic in the stack communicates bidirectionally to the ics of the same type above and below it via currents. there is no limit to the stack height. large common mode voltage differences are handled by each ltc3300-1. the microprocessor in the bms system communicates only with the bottom ic in the stack and subsequently all of the ics use the same fixed internal address. the ltc3300-2 employs an spi - compatible serial interface in which each ic has a unique 5- bit pin-strapped address . the microprocessor in the bms system communicates directly with every ic in the stack with common mode voltage differences handled by digital isolators or opto- couplers. because of the 5- bit address, the stack height is limited to 32 ltc3300-2 ics or 192 cells (~800v). there are 5 pins which have a different assignment, all of them serial interface related. see table 10 for a summary of differences between ltc3300-1 and ltc3300-2 table 10. ltc3300-1 vs ltc3300-2 differences ltc3300-1 ltc3300-2 high side current mode spi pins csbo, scko, sdoi none where am i in the stack? pins v mode , tos none* spi address 10101 (fixed) a 4 a 3 a 2 a 1 a 0 (pin strapped) maximum height of batter y stack unlimited 32 6 = 192 cells gnd (v C ) pin current in shutdown/suspend 23.5a 14a *ltc3300-2 has v mode = tos = 1 fixed internally. each ic in the stack thinks it is both top-of-stack and bottom-of-stack. consequently, opto-couplers or digital isolators are needed to communicate between the p and each ic. downloaded from: http:///
ltc3300-2 33 33002f for more information www.linear.com/ltc3300-2 figure 12. internal protection diodes applications information 48 v reg 20 wdt 19 sdo 18 sdi 17 scki 16 47 csbi a4 ltc3300-2 44 a1 45 a2 46 a3 43 a0 40 boost + 41 boost C 38 g6p 37 i6pc5 39 c6 42 boost 15 ctrl 14 rtonp 13 rtons 1 g6s 2 i6s 3 g5s 4 i5s 5 g4s 6 i4s 7 g3s 8 i3s 9 g2s z clamp z clamp 10 i2s 11 g1s 12 i1s 33002 f12 36 35 g5p 34 i5pc4 33 32 g4p 31 i4pc3 30 29 g3p 28 i3pc2 27 26 g2p 25 i2pc1 24 23 g1p 22 i1p 4 exposed pad 21 v C 49 downloaded from: http:///
ltc3300-2 34 33002f for more information www.linear.com/ltc3300-2 applications information how to calculate the crcone simple method of computing an n- bit crc is to perform arithmetic modulo-2 division of the n+1 bit characteristic polynomial into the m bit message appended with n ze - ros ( m+n bits). arithmetic modulo-2 division resembles normal long division absent borrows and carries. at each intermediate step of the long division, if the leading bit of the dividend is a 1, a 1 is entered in the quotient and the dividend is exclusive-ored bitwise with the divisor. if the leading bit of the dividend is a 0, a 0 is entered in the quotient and the dividend is exclusive-ored bitwise with n zeros. this process is repeated m times. at the end of the long division, the quotient is disregarded and the n-bit remainder is the crc. this will be more clear in the example to follow. for the crc implementation in the ltc3300-2, n = 4 and m = 12. the characteristic polynomial employed is x 4 + x + 1, which is shorthand for 1 x 4 + 0 x 3 + 0 x 2 + 1 x 1 + 1 x 0 , resulting in 10011 for the divisor. the message is the first 12 bits of the balance command. suppose for example the desired balance command calls for simultaneous charging of cell 1 and synchronous discharging of cell?4. the 12- bit message ( msb first) will be 110000010000. appending 4 zeros results in 1100000100000000 for the dividend. the long division is shown in figure 13 a with a resultant crc of 1101. note that the crc bits in the write balance command are inverted. thus the correct 16- bit balance command is 1100000100000010. figure?13b shows the same long division procedure being used to check the crc of data ( command or status) read back from the ltc3300-2. in this scenario, the remainder after the long division must be zero (0000) for the data to be valid. note that the readback crc bits must be inverted in the dividend before performing the division. an alternate method to calculate the crc is shown in figure 14 in which the balance command bits are input to a combinational logic circuit comprised solely of 2- input exclusive-or gates. this brute force implementation is easily replicated in a few lines of c code. figure 13. (a) long division example to calculate crc for writes. (b) long division example to check crc for reads 1 1 0 1 0 1 1 0 1 0 1 11 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 1 1 0 1 0 0 1 1 remainder = 1 1 0 1 = 4-bit crc 1 1 0 1 0 1 1 0 1 0 1 11 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 1 0 1 0 0 0 0 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 remainder = 0 33002 f13 0 0 1 0 = 4-bit crc inverted readback = 1100000100000010 dividend = 1100000100001101 (b) (a) downloaded from: http:///
ltc3300-2 35 33002f for more information www.linear.com/ltc3300-2 applications information serial communication using the ltc6803 and ltc6804 the ltc3300-2 is compatible with and convenient to use with all lt c monitor chips, such as the ltc6803 and ltc6804. figure 17 in the typical applications section shows the serial communications connections for a joint ltc3300-2/ltc6803-2 bms using a common micropro - cessor spi port. the scki, sdi, and sdo lines of the low- ermost ltc3300-2 and ltc6803-2 are tied together. the csbi lines, however, must be separated to prevent talking to both ics at the same time. this is easily accomplished by using one of the gpio outputs from the ltc6803-2 to gate and invert the csbi line to the ltc3300-2. in this setup, communicating to the ltc6803-2 is no different than without the ltc3300-2, as the gpio1 output bit is normally high. to talk to the ltc3300-2, written commands must be bookended with a gpio1 negation write to the ltc6803-2 prior to talking to the ltc3300-2 and with a gpio1 assertion write after talking to the ltc3300-2. communication to all non - ground referred ltc3300-2 and ltc6803-2 ics is done through digital isolators. the typical application shown on the back page of this data sheet shows the serial communication connections for a joint ltc3300-2/ltc6804-2 bms. each stacked 12-cell module contains two ltc3300-2 ics and a single ltc6804-2 monitor ic . . the ltc6804-2 in the module is configured to provide an effective spi port output at its gpio3, gpio4, and gpio5 pins which connect directly to the low side communication pins ( csbi, sdi=sdo, scki) of the lower ltc3300-2. the upper ltc3300-2 in each module receives its serial communication via a digital isolator from the lower ltc3300-2. communication to the lowermost ltc6804-2 and between monitor chips is done via the ltc6820 and the isospi? interface. in this application, unused battery cells can be shorted from the bottom of any module ( i.e., outside the module, not on the module board) as shown without any decrease in monitor accuracy. figure 14. combinational logic circuit implementation of the crc calculator crc [3] crc [3]crc [2] crc [1] crc [0] 33002 f14 d6b ? ?? ? d5bd3b d1b d2a d5a d3a d1a d4b d2b d4a d6a crc [2] crc [1] crc [0] downloaded from: http:///
ltc3300-2 36 33002f for more information www.linear.com/ltc3300-2 pcb layout considerations the ltc3300-2 is capable of operation with as much as 40v between boost + and v C . care should be taken on the pcb layout to maintain physical separation of traces at different potentials. the pinout of the ltc3300-2 was chosen to facilitate this physical separation. there is no more than 8.4 v between any two adjacent pins with the exception of one instance ( boost to boost C ). in this instance, the boost pin is pin-strapped in the applica- tion to v C or v reg and does not need to route far from the ltc3300-2. the package body is used to separate the highest voltage (e.g., 25.2v) from the lowest voltage (0v). as an example, figure?15 shows the dc voltage on each pin with respect to v C when six 4.2 v battery cells are connected to the ltc3300-2.additional good practice layout considerations are as follows: 1. the v reg pin should be bypassed to the exposed pad and to v C , each with 1 f or larger capacitors as close to the ltc3300-2 as possible. applications information 2. the differential cell inputs ( c6 to c5, c5 to c 4, , c1 to exposed pad) should be bypassed with a 1 f or larger capacitor as close to the ltc3300-2 as possible. this is in addition to bulk capacitance present in the power stages. 3. pin 21 ( v C ) is the ground sense for current sense resis- tors connected to i1s-i6s and i1p ( seven resistors). pin 21 should be kelvined as well as possible with low impedance traces to the ground side of these resistors before connecting to the ltc3300-2 exposed pad. 4. cell inputs c1 to c5 are the ground sense for current sense resistors connected to i2p-i6p ( five resistors). these pins should be kelvined as well as possible with low impedance traces to the ground side of these resistors. 5. the ground side of the maximum on-time setting resis - tors connected to the rtons and rtonp pins should be kelvined to pin 21 ( v C ) before connecting to the ltc3300-2 exposed pad. 6. trace lengths from the ltc3300-2 gate drive outputs (g1s-g6s and g1p-g6p) and current sense inputs (i1s-i6s and i1p-i6p) should be as short as possible. 7. the boosted gate drive components ( diode and ca - pacitor), if used, should form a tight loop close to the ltc3300-2 c6, boost + , and boost C pins. 8. for the external power components ( transformer, fets and current sense resistors), it is important to keep the area encircled by the two high speed current switching loops ( primary and secondary) as tight as possible. this is greatly aided by having two additional bypass capacitors local to the power circuit: one differential cell to cell and one from the transformer secondary to local v C . a representative layout incorporating all of these recom- mendations is implemented on the dc2064a demo board for the ltc3300-1 companion product ( with further ex- planation in its accompanying demo board manual). to accommodate the ltc3300-2, only minor modifications to pins 43 to 47 connections need to be made. pcb layout files (.grb) are also available from the factory. figure 15. typical pin voltages for six 4.2v cells ltc3300-2 (exposed pad = 0v) 0v to 4.8v 0v 0v to 4.8v 0v 0v to 4.8v 0v 0v to 4.8v 0v 0v to 4.8v 0v 0v to 4.8v 0v 21v16.8v to 25.2v 16.8v 16.8v 12.6v to 21v 12.6v 12.6v 8.4v to 16.8v 8.4v 8.4v 4.2v to 12.6v 4.2v g6spin 1i6s g5s i5s g4s i4s g3s i3s g2s i2s g1s i1s c5 g5p i5p c4 g4p i4p c3 g3p i3p c2 g2p i2p v reg a4a3 a2 a1 a0 boost boost C boost + c6 g6p i6p 1.2v1.2v 0v/4.8v 0v to 4.8v0v to 4.8v 0v to 4.8v 0v to 4.8v 0v to 4.8v 0v0v 0v to 8.4v 4.2v rtons rtonp ctrl csbi scki sdi sdo wdt v C i1pg1p c1 4.8v 0v/4.8v 0v/4.8v 0v/4.8v 0v/4.8v 0v/4.8v 0v/4.8v 21v to 25.2v 25.2v to 29.4v 25.2v 21v to 29.4v 21v 33002 f15 downloaded from: http:///
ltc3300-2 37 33002f for more information www.linear.com/ltc3300-2 typical applications 1:11:1 1:1 1:1 ?? ? ? ? ?? ? ?? ? ?? ? 25m 10h 10h c6 0.1f 10f cell 6 g6p i6p ltc3300-2 v reg boost rtons isolation boundary rtonp boost + 6.8 boost C ctrl v C 41.2k 33002 f16 28k 10f ?? ? ?? ? + ? 25m 10h 10h c5 10f cell 5 g5p i5p c4 + ? 25m 10h 10h c2 c3 10f cell 2 g2p i2p + ? 25m nc 10h 10h c1 10f cell 1 g1p i1p g1s-g6s i1s-i6s + isolated 12v lead acid auxiliary cell + ?? ? ?? ? ?? ? serial communication related pins a4a3 a2 a1 a0 csbi scki sdi sdo wdt figure 16. ltc3300-2 unidirectional discharge-only balancing application to charge an isolated auxiliary cell downloaded from: http:///
ltc3300-2 38 33002f for more information www.linear.com/ltc3300-2 typical applications figure 17. lt c 3300-2/ lt c 6803-2 battery and serial communication connections for a 24-cell stack + c5c4 c3 c2 c1 v reg csbiscki sdi sdo c6 gpio2gpio1 csbiscki sdi sdo c11c10 c9 c8 c7 c5 c4 c3 c2 c1 c6 c12 top of battery stack ltc3300-2 address = 00011 ltc6803-2 address = 0001 v C c vreg4 digital isolator cell 24 + cell 23 + cell 22 + cell 21 + cell 20 + cell 19 + cell 18 + cell 17 + cell 16 + cell 15 + cell 14 + cell 13 c5c4 c3 c2 c1 v reg v reg csbiscki sdi sdo c6 v C v C c vreg3 c vreg6 + nc ncnc 33002 f17 gpio2gpio1 csbiscki sdi sdo c11c10 c9 c8 c7 c5 c4 c3 c2 c1 c6 c12 ltc6803-2 address = 0000 cell 12 + cell 11 + cell 10 + cell 9 + cell 8 + cell 7 + cell 6 + cell 5 + cell 4 + cell 3 v reg1 v reg5 + cell 2 + cell 1 v reg v C c vreg5 c vreg2 v reg1 or v reg5 c vreg1 v1 + v2 + v1 C v2 C cs clk mosi mpu 3v digital isolator moso digital isolator digital isolator digital isolator ltc3300-2 address = 00010 c5c4 c3 c2 c1 v reg csbiscki sdi sdo c6 v C ltc3300-2 address = 00001 c5c4 c3 c2 c1 v reg csbiscki sdi sdo c6 v C ltc3300-2 address = 00000 downloaded from: http:///
ltc3300-2 39 33002f for more information www.linear.com/ltc3300-2 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. 7.00 0.10 (4 sides) note:1. drawing conforms to jedec package outline mo-220 variation (wkkd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark(see note 6) pin 1 chamfer c = 0.35 0.40 0.10 48 47 12 bottom viewexposed pad 5.50 ref (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uk48) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 5.50 ref (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline 5.15 0.10 5.15 0.10 5.15 0.05 5.15 0.05 r = 0.10 typ uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704 rev c) downloaded from: http:///
ltc3300-2 40 33002f for more information www.linear.com/ltc3300-2 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. lxe48 lqfp 0113 rev c 0 C 7 11 C 13 0.45 C 0.75 1.00 ref 11 C 13 1 48 1.60 max 1.35 C 1.45 0.05 C 0.15 0.09 C 0.20 0.50 bsc 0.17 C 0.27 gauge plane 0.25 note:1. dimensions are in millimeters 2. dimensions of package do not include mold flash. mold flash shall not exceed 0.25mm on any side, if present 3. pin-1 indentifier is a molded indentation, 0.50mm diameter 4. drawing is not to scale r0.08 C 0.20 7.15 C 7.25 5.50 ref 1 3625 12 5.50 ref 7.15 C 7.25 48 13 24 37 c0.30 package outline recommended solder pad layout apply solder mask to areas that are not soldered bottom of packageexposed pad (shaded area) side view section a C a 0.50 bsc 0.20 C 0.30 1.30 min 9.00 bsc a a 7.00 bsc 1 12 7.00 bsc 3.60 0.10 3.60 0.10 9.00 bsc 48 37 13 24 37 13 24 36 36 25 25 see note: 3 c0.30 C 0.50 3.60 0.05 3.60 0.05 c0.30 lxe package 48-lead plastic exposed pad lqfp (7mm 7mm) (reference ltc dwg #05-08-1832 rev c) 12 e3 ltcxxxx lx-es q_ _ _ _ _ _ xxyy tray pin 1 bevel package in tray loading orientation component pin a1 downloaded from: http:///
ltc3300-2 41 33002f for more information www.linear.com/ltc3300-2 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 12/13 add new bullet integrates seamlessly with the ltc680x family of multicell battery stack monitors change part number xf0036-ep135 to xf0036-ep13s 1 29 downloaded from: http:///
ltc3300-2 42 33002f for more information www.linear.com/ltc3300-2 linear technology corporation 2013 lt 0813 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3300-2 related parts part number description comments ltc3300-1 high efficiency bidirectional mulitcell battery balancer allows serial ports of multiple devices to be daisy-chained without opto-couplers or isolators ltc6801 independent multicell battery stack monitor monitors up to 12 series-connected battery cells for undervoltage or overvoltage, companion to ltc6802, ltc6803 and ltc6804 ltc6802-1/ltc6802-2 multicell battery stack monitors measures up to 12 series-connected battery cells, 1st generation: superseded by the ltc6803 and ltc6804 for new designs ltc6803-1/ltc6803-3 ltc6803-2/ltc6803-4 multicell battery stack monitors measures up to 12 series-connected battery cells, 2nd generation: functionally enhanced and pin compatible to the ltc6802 ltc6804-1/ltc6804-2 multicell battery monitors measures up to 12 series-connected battery cells, 3rd generation: higher precision than ltc6803 and built-in isospi interface ltc6820 isospi isolated communications interface provides an isolated interface for spi communication up to 100m using a twisted pair, companion to the ltc6804 typical application 9 cells 12 cells 12-cellmodule 2 iso in gpio5gpio4 gpio3 scki sdi sdo csbi ltc6804-2 data ltc3300-2 ltc3300-2 digital isolator address = 00011 address = 00001 address = 00000 address = 00010 address = 0001 iso in gpio5gpio4 gpio3 ltc6804-2 address = 0000 12-cellmodule 1 iso 33002 ta02 spi 4 scki sdi sdo csbi ltc6820 isospi ltc3300-2 ltc3300-2 4 digital isolator 4 address = 00001 address = 00000 ltc3300-2/ltc6804-2 serial communication connections downloaded from: http:///

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